Union Minister for Electronics & IT, Railways, and Information & Broadcasting, Shri Ashwini Vaishnaw, today inaugurated two advanced semiconductor design facilities of Renesas Electronics India Private Limited, located in Noida and Bengaluru. Marking a milestone in India's semiconductor journey, the Minister announced that these centres include the country鈥檚 first-ever facility dedicated to designing next-generation 3 nanometre (nm) chips.
鈥淒esigning at 3nm is truly cutting-edge. India has already worked on 7nm and 5nm nodes, but this takes us into a new league,鈥� said Shri Vaishnaw, highlighting the significance of the new centre in the global semiconductor landscape.
He also outlined India鈥檚 comprehensive semiconductor strategy, which spans design, fabrication, ATMP (Assembly, Testing, Marking, and Packaging), equipment, and material supply chains. Citing recent industry confidence at global events like Davos, he noted major investments from firms such as Applied Materials and Lam Research.
To nurture talent, Shri Vaishnaw announced a new semiconductor learning kit for engineering students to enhance practical skills. Over 270 academic institutions that have received advanced Electronic Design Automation (EDA) tools under the India Semiconductor Mission will now also benefit from these hands-on hardware kits. 鈥淲e are developing not just infrastructure, but future-ready engineers,鈥� he added.
The Minister commended CDAC and the ISM team for their swift implementation and credited Prime Minister Narendra Modi鈥檚 strategic focus on semiconductors under the Aatmanirbhar Bharat initiative. 鈥淚n just three years, India鈥檚 semiconductor sector has evolved from an idea to a global force,鈥� he stated, adding that booming demand across smartphones, laptops, medical devices, defence, and automotive sectors makes this progress timely.
Renesas CEO & MD Shri Hidetoshi Shibata called India a 鈥渟trategic cornerstone鈥� for the company. He reaffirmed Renesas鈥� commitment to building end-to-end semiconductor capabilities in India, from architecture to testing, and to supporting over 250 academic institutions and numerous startups through schemes such as Chips to Startup (C2S) and the Design Linked Incentive (DLI) Scheme.
He emphasised that India鈥檚 engineering talent and Indo-Japan cooperation would help redefine the global semiconductor ecosystem.
